This invention relates to programmable logic resources. More particularly, this invention relates to synchronizing the transfer of data into programmable logic resources.
A programmable logic resource is a general-purpose integrated circuit that is programmable to perform any of a wide range of logic tasks. Known examples of programmable logic resource technology include programmable logic devices (PLDs), complex programmable logic devices (CPLDs), erasable programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), and field programmable gate arrays (FPGAs).
Input-output (I/O) circuitry is provided to facilitate the transfer of data into programmable logic resources. The I/O circuitry serves as an interface between programmable logic resource core circuitry and circuitry external to the programmable logic resource.
Data is often transferred from external circuitry to programmable logic resource core circuitry over multiple channels. The I/O circuitry can include a dynamic phase alignment circuit, a phase synchronizer, and a data realigner associated with each channel, and one phase-locked loop (PLL) circuit. The PLL circuit receives as input a forwarded clock and generates multiple clock phases based on the forwarded clock. The multiple clock phases and data signals are sent to the dynamic phase alignment circuit associated with each channel. The dynamic phase alignment circuit operates to minimize skew in the data signal relative to the clock to allow for data to be correctly transferred into the programmable logic resource core circuitry. Each dynamic phase alignment circuit generates a recovered clock based on the multiple clock phases generated by the PLL circuit, aligns the data signal to the recovered clock to produce retimed data, converts the retimed data to parallel data having a suitable number of bits (e.g., 8 bits, 10 bits), and outputs the parallel data at the same frequency as the programmable logic resource core clock but with a different phase. The parallel data is then sent to the phase synchronizer which includes a 4-bit deep first-in first-out (FIFO) buffer. The phase synchronizer synchronizes the phase of the parallel data to the phase of the programmable logic resource core clock for output to a data realigner. The data realigner, which can change the boundary of the synchronized parallel data, outputs data for transmission through the corresponding channel to the programmable logic resource core circuitry.
There are several limitations with using phase synchronizers to synchronize the transfer of data into programmable logic resources. Implementing a phase synchronizer results in clock latency. For a 4-bit deep FIFO buffer, up to four cycles of latency can be introduced in the data path. In addition, the phase synchronizer requires a large amount of logic to implement, which increases the area and thus cost of the programmable logic resource.
In view of the foregoing, it would be desirable to provide a more time-efficient and area-efficient approach in synchronizing the transfer of data into programmable logic resources without the use of phase synchronizers.